Method and device for implementing Viterbi decoding

ABSTRACT

The disclosure provides a method and device for implementing Viterbi decoding. The method comprises the following steps: calculating branch path measurement values of received code words and reference code words; parallel accumulating the branch path measurement values and measurement values corresponding to states to obtain accumulated values according to a state transition diagram, selecting a maximum accumulated value as a new measurement value of a next state, and saving all survival path selection results until data for decoding ends; and starting traceback from a final state to obtain decoded data according to the survival path selection results. In the disclosure, by modifying the traditional serial or serial-parallel mixed mode for calculating accumulated path measurement values to a multi-path fully-parallel calculation mode, the throughput rate of the system data is improved, and the decoding delay is merely in μs level.

FIELD OF THE INVENTION

The present disclosure relates to the field of communication, inparticular to a method and a device for implementing Viterbi decoding.

BACKGROUND OF THE INVENTION

In wireless transmission, the received data contains a large amount oferror codes as the channel is relatively poor. Therefore, transmissionsignals must be encoded and error corrected. The purpose of channelencoding is to resist against various noises and interferences duringthe transmission process, by adding redundant information manually, asystem is provided with a capability of automatic error correction, soas to guarantee the reliability of digital transmission. With thedevelopment of the wireless digital communication technology and theappearance of high-rate strong-abruptness services, people propose moredemanding requirements on the error correction encoding technology.

At first, error code correction is mainly concentrated in linear blockcodes based on algebraic theory, and then Hamming codes, RS codes,cyclic codes or the like. However, effect in solving practical problemsis limited. Register is introduced into the encoding process ofconvolutional codes appearing in the fifties, and correlation betweencode elements is added, so that a higher encoding gain than that ofblock codes is obtained under a same complexity. There are three gridtermination policies for convolutional codes:

Direct truncation: no any information about the final state of grid isprovided to the decoder;

Zero termination: tail bit 0 is added behind the information bit andthen encoding is carried out, in order to ensure that the grid returnsto a specific state 0;

Tail biting: it has a special way—zero termination, the main feature ofwhich is that no tail bit needs to be added. Tail biting means that:before one code block is encoded, the initial state of the convolutionalcode encoder is set as the final several bits of the code block, forcyclic convolutional codes, after the encoding process ends, the encoderreturns to the initial state, so the decoding grid may be regarded as acircle, initialization may be realized in the case of decoding at anyposition of the circle, therefore, the corresponding decoding may beregarded as spinning cyclic decoding.

For convolutional encoding, there are many corresponding decodingalgorithms, but among these algorithms, the most effective and mostpractical decoding algorithm is maximum likelihood decoding, i.e.,Viterbi decoding algorithm. In order to improve the code rate ofconvolutional codes and meet the application of high-speed systems suchas Long Term Evolution (LTE), tail biting convolutional encoder isemployed in most solutions, the corresponding convolutional decoderneeds larger storage space, and the complexity of calculation is alsohigher.

SUMMARY OF THE INVENTION

The main purpose of the present disclosure is to provide a method anddevice for implementing Viterbi decoding, in order to save the storagespace of calculation for the convolutional decoding and improve theworking efficiency of decoding.

The present disclosure provides a method for implementing Viterbidecoding, comprising:

Calculating branch path measurement values of received code words andreference code words;

Parallel accumulating the branch path measurement values and measurementvalues corresponding to states to obtain accumulated values according toa state transition diagram, selecting a maximum accumulated value as anew measurement value of a next state, and saving all survival pathselection results until data for decoding ends; and

Starting traceback from a final state to obtain decoded data accordingto the survival path selection results.

Preferably, before calculating the branch path measurement values of thereceived code words and the reference code words, the method furthercomprises:

Storing the data for decoding, which is input externally, in a mode ofinterleaved memory; and reading the data for decoding according to anexternal decoding instruction.

Preferably, parallel accumulating the branch path measurement values andthe measurement values corresponding to the states to obtain theaccumulated values according to the state transition diagram, selectingmaximum accumulated value as the new measurement value of the nextstate, and saving all survival path selection results until the data fordecoding ends comprises:

Multi-path fully-parallel accumulating the branch path measurementvalues and the measurement values corresponding to the states to obtainthe accumulated values according to the state transition diagram;

Selecting the maximum accumulated value as the new measurement value ofthe next state according to the add-compare-select rule, and saving allsurvival path selection results; and

Returning to execute a next accumulation operation when an accumulationtime is less than a preset accumulation time; and ending theaccumulation flow when the accumulation time is more than or equal tothe preset accumulation time.

Preferably, after multi-path fully-parallel accumulating the branch pathmeasurement values and the measurement values corresponding to thestates to obtain the accumulated values according to the statetransition diagram, the method further comprises:

Subtracting 1 from the secondary highest bit in the significant bits ofeach accumulated value to obtain a new accumulated value, if the highestbit in the significant bits of the accumulated value corresponding tostate 0 is 1, then using the new accumulated value as the result of thisaccumulation operation.

Preferably, the traceback depth is two times of the encoding length.

The present disclosure provides a device for implementing Viterbidecoding, comprising: a branch path measurement module, anadd-compare-select module and a traceback module; wherein,

The branch path measurement module is configured to calculate branchpath measurement values of received code words and reference code words;

The add-compare-select module is configured to parallel accumulate thebranch path measurement values and measurement values corresponding tostates to obtain accumulated values according to a state transitiondiagram, select a maximum accumulated value as a new measurement valueof a next state, and save all survival path selection results until datafor decoding ends; and

The traceback module is configured to start traceback from a final stateto obtain decoded data according to the survival path selection results.

Preferably, the device further comprising:

An input data storage module, configured to store the data for decoding,which is input externally, in a mode of interleaved memory; and read thedata for decoding according to an external decoding instruction.

Preferably, the add-compare-select module comprises: an accumulationunit, a selection unit, a survival path storage unit and a judgmentunit; wherein,

The accumulation unit is configured to multi-path fully-parallelaccumulate the branch path measurement values and measurement valuescorresponding to the states to obtain the accumulated values accordingto the state transition diagram;

The selection unit is configured to select the maximum accumulated valueas the new measurement value of the next state according to theadd-compare-select rule;

The survival path storage unit is configured to save all survival pathselection results; and

The judgment unit is configured to return to execute a next accumulationoperation of the accumulation unit when an accumulation time is lessthan a preset accumulation time; and end the accumulation flow when theaccumulation time is more than or equal to the preset accumulation time.

Preferably, the add-compare-select module further comprises:

An anti-overflow unit, configured to subtract 1 from the secondaryhighest bit in the significant bits of each accumulated value to obtaina new accumulated value, if the highest bit in the significant bits ofthe accumulated value corresponding to state 0 is 1, then use the newaccumulated value as the result of this accumulation operation.

Preferably, the traceback depth employed by the traceback module is twotimes of the encoding length.

In the disclosure, by modifying the traditional serial orserial-parallel mixed mode for calculating the accumulated pathmeasurement values to a multi-path fully-parallel calculation mode, thethroughput rate of the system data is improved, and the decoding delayis merely in us level.

In the disclosure, the original mode of sliding window traceback is alsochanged, decoding result is output by one traceback, the traceback depthis two times of the encoding length, but the second section tracebackdata in the traceback depth is only valid. The accumulated values andstate measurement values needn't to be stored. The method is simple andefficient, and the performance of the system is also improved.

The disclosure further proposes a novel anti-overflow mode ofaccumulated path measurement value, the implementation is easier, andthe bit width of the accumulated path measurement value (also referredto as the accumulated value) may be reduced.

In the disclosure, the input data for decoding is stored in aninterleaved mode, data input and decoding may be performedsimultaneously, so that the problem of processing delay caused bywaiting for decoding is solved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram of a method for implementing Viterbi decodingaccording to the embodiments of the present disclosure;

FIG. 2 is a structure diagram of a tail biting convolutional encoderaccording to the related art of the present disclosure;

FIG. 3 is a state transition diagram of a tail biting convolutionalencoder according to the related art of the present disclosure;

FIG. 4 is a flow diagram of accumulated path measurement valuesaccording to one embodiment of a method for implementing Viterbidecoding of the present disclosure;

FIG. 5 is a flow diagram of accumulated path measurement valuesaccording to another embodiment of a method for implementing Viterbidecoding of the present disclosure;

FIG. 6 is a flow diagram of a method for implementing Viterbi decodingaccording to still another embodiment of the present disclosure;

FIG. 7 is a structure diagram of an interleaved memory in a method forimplementing Viterbi decoding according to one embodiment of the presentdisclosure;

FIG. 8 is a structure diagram of a device for implementing Viterbidecoding according to one embodiment of the present disclosure;

FIG. 9 is a structure diagram of an add-compare-select module in adevice for implementing Viterbi decoding according to one embodiment ofthe present disclosure;

FIG. 10 is a structure diagram of an add-compare-select module in adevice for implementing Viterbi decoding according to another embodimentof the present disclosure; and

FIG. 11 is a structure diagram of a device for implementing Viterbidecoding according to still another embodiment of the presentdisclosure.

The implementation of the purpose, function features and advantages ofthe disclosure will be further described with reference to drawings andembodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

It should be understood that, specific embodiments described herein areonly used for explaining the disclosure, not for limiting thedisclosure.

FIG. 1 is a flow diagram of a method for implementing Viterbi decodingaccording to the embodiment of the present disclosure.

In the present embodiment, the method for implementing Viterbi decodingcomprises the following steps:

Step S10: Calculating the branch path measurement values of receivedcode words and reference code words;

The received code words are the data for decoding, and the referencecode words are the state output values of the encoder. The state outputvalues of the encoder and the data for decoding are correlativelycalculated to obtain the branch path measurement values.

The present embodiment is mainly used for decoding error correctioncodes in a data mobile communication system, for example, the3rd-Generation (3G) mobile communication technology and Long TermEvolution (LTE) project. Details description will be given below bytaking the tail biting convolutional encoder provided in the 3GPPTS36.212 standard as example.

With reference to FIG. 2, for the tail biting convolutional encoderprovided in the 3GPP TS36.212 standard, there are total six shiftregisters D, the code rate is ⅓, the input signal at each moment isC_(k), the output corresponding to each moment is d_(k) ⁽²⁾, d_(k) ⁽¹⁾and d_(k) ⁽⁰⁾ in a descending order, correspondingly, the octal encodingpolynomial is G₂, G₁ and G₀, therefore, there are 2⁶=64 states duringeach calculation, respectively: S₀, S₁, S₂, . . . , S₆₃, and the sixregisters are expressed by vector: dd[5:0], wherein dd[0] is the triggercorresponding to input.

dd changes during the encoding process: ddt[5:0]={ddt−1[5:0], din}, fromthis formula, it may be seen that there are two dds reaching one S_(t)state: {0, ddt−1 [4:0]} and {1, ddt−1[4:0]}, and they meet:ddt[5:1]=ddt−1[4:0], ddt[0]=din. It also may be seen that both {0,ddt−1[4:0]} and {1, ddt−1[4:0]} may reach two states {ddt−1 [4:0], 0}and {ddt−1 [4:0], 1}.

Specifically, during the convolutional encoding process, at T moment,two states S_(k) and S_(k+32) (k=0 to 31) may reach states S_(2k) andS_(2k+1), S_(2k) is corresponding to input 0, and S_(2k+1) iscorresponding to input 1. The highest bits of S_(k) and S_(k+)32 arerespectively corresponding to 0 and 1, as shown in the encoding/decodingstate transition diagram in FIG. 3. For example, by related calculation,it may be known that the branch path measurement values from S_(k) toS_(2k) and from S_(k) to S_(2k+1) are respectively 5 and 3, and thebranch path measurement values from S_(k+32) to S_(2k) and from S_(k+32)to S_(2k+1) are respectively 13 and 10.

Step S11: Parallel accumulating the branch path measurement values andthe measurement values corresponding to states to obtain accumulatedvalues according to a state transition diagram, selecting the maximumaccumulated value as the new measurement value of the next state, andsaving all survival path selection results until the data for decodingends;

With reference to FIG. 4, Step S11 may specifically comprise:

Step A1: Multi-path fully-parallel accumulating the branch pathmeasurement values and the measurement values corresponding to thestates to obtain accumulated value according to the state transitiondiagram;

According to the state transition diagram, by means of multi-path (forexample, 32-path) fully-parallel, the branch path measurement values andthe measurement values corresponding to the states are accumulated toobtain accumulated values. For example, at T−1 moment, the measurementvalue of S_(k) is 26, the measurement value of S_(k+32) is 15, and thebranch path measurement values from S_(k) to S_(2k) and from S_(k) toS_(2k+1) are respectively 5 and 3, while the branch path measurementvalues from S_(k+32) to S_(2k) and from S_(k+32) to S_(2k+1) arerespectively 13 and 10, by accumulating the branch path measurementvalues and the measurement values corresponding to the states it may beknown that, the path accumulated values reaching S_(2k) are respectively26+5=31 and 15+13=28, and the path accumulated values reaching S_(2k+1)are respectively 26+3=29 and 15+10=25.

Step A2: Selecting the maximum accumulated value as the new measurementvalue of the next state according to the add-compare-select rule;

According to the add-compare-select rule, the path accumulated values oftwo branches reaching a same state are compared, the maximum pathaccumulated value is selected as the new measurement value of the state,the selection results are recorded until the data for decoding ends. Forexample, according to Step A2, the maximum path accumulated value 31will be selected as the new measurement value of S_(2k), and the maximumpath accumulated value 29 will be selected as the new measurement valueof S_(2k+1). Therefore, at T moment, the measurement values of S_(2k)and S_(2k+1) are respectively 31 and 29, which are used as measurementvalues corresponding to states for accumulation operation at T+1 moment.

Step A3: Saving all survival path selection results;

According to the selection results in Step A2, all survival pathselection results are saved to form one survival path, according towhich the initial state is backtracked latter.

Step A4: Judging whether the accumulation time is less than a presetaccumulation time, if so, returning to execute Step A1; otherwise,ending the accumulation flow.

The preset accumulation time depends on both the length of the codeblock and the circulation time of the external decoding.

Step S12: Starting traceback from the final state to obtain the decodeddata according to the survival path selection results.

After the data for decoding ends, the corresponding survival pathselection results are obtained by Step S11, in Step S12, traceback maybe started from the final state to obtain the decoded data. The finalstate may be state 0, and also may be any state.

In this step, as the encoding mode of the encoder has been determinedbefore encoding, the reference code words or the called encodingpolynomial have been determined, how to perform butterfly accumulationin Step S11 according to the branch path measurement values obtained inStep S10 depends on calculation and selection of the states of thereference code words and the input code words, and the selection has tobe performed in the add-compare-select interior. While in the presentdisclosure, according to add-compare-select fully-parallel accumulationand the state transition feature of the encoder, a lot of circuits for32-path parallel calculation fixed option may be reduced, and the systemresources may be saved.

In the present embodiment, by modifying the traditional serial orserial-parallel mixed mode for calculating the accumulated pathmeasurement values to a multi-path fully-parallel calculation mode, thethroughput rate of the system data is improved, and the decoding delayis merely in us level.

In the present embodiment, when the accumulated path measurement valueis calculated, a large amount of resources will be wasted if the bitwidth is not limited. For example, four times of decoding circulationare performed, the length of the code block is 128, the bit width of theinput data for decoding is 8-bit, so the bit width of the accumulatedpath measurement values is 19-bit (2⁸*3*128*4=2¹⁹), at least 64accumulated path measurement value registers are needed, so that thewaste of resources is relatively serious. Therefore, in order to reducethe waste of resources, with reference to FIG. 5, after Step A2, themethod may further comprise:

Step A5: Subtracting 1 from the secondary highest bit in the significantbits of each accumulated value to obtain a new accumulated value, if thehighest bit in the significant bits of the accumulated path measurementvalue corresponding to state 0 is 1, then using the new accumulatedvalue as the result of this accumulation operation.

First, it is necessary to judge whether the highest bit in thesignificant bits (if signed digits are available, significant bits aredata bits other than sign bits) of the accumulated path measurementvalue corresponding to state 0 is 1, if so, the secondary highest bit inthe significant bits of each accumulated values is subtracted by 1, thatis, the whole measurement value is simply normalized to zero. Forexample, by taking 14-bit accumulated path measurement value as example,when distance0[12] is zero, normal operation is performed, and thegenerated subtraction enabling signal sub_en is in low level; whendistance0[12] is 1, the generated subtraction enabling signal sub_en isin high level, so that all survival paths are subtracted by 0x800(hexadecimal), i.e., the secondary highest bit in the significant bitsof distance0, to prevent the overflow of the accumulated measurementvalue effectively.

The traditional anti-overflow step mainly depends on the selection ofthe fixed value, and it is necessary to compare all path measurementvalues and select the minimum one as the fixed value, instead, theanti-overflow step in the present embodiment may save a lot ofcomparison and selection circuits and the subtraction circuit is quitesimple as it is only aimed at subtracting the three top bits of theaccumulated measurement value by 1.

In the present embodiment, in Step S12, the traceback depth is two timesof the encoding length. The specific traceback process is: from StepS11, the initial state of traceback may be obtained as max_num[5:0]=0,the front state of the initial state is max_num[5:0]={qqq[max_num],max_num[5:1]}, herein, qqq is the recorded 64-bit survival path value.When the recorded survival path selection result qqq has to be selectedfor traceback, the traceback depth is about 2*block_size, the outputresult of decoding after traceback is dec_bit=max_num[0]. When data isoutput, traceback data obtained in a depth the first time of theencoding length is abandoned, only traceback data obtained in a depththe second time of the encoding length is used, therefore, tracebackdata obtained in a depth only one time of the encoding length is stored,no much thing is added in terms of resources. The reason for theapplication of traceback depth that is two times of the encoding lengthis that, normal convolutional codes are replaced with tail bitingconvolutional codes in the high-speed decoding system, after emulation,it is found that the performance of the decoder is improved by 0.2 db to0.3 db in comparison with traceback in a depth that is one time of theencoding length, therefore, in the present disclosure, the applicationof traceback depth that is two times of the encoding length guaranteesthe performance of the system. Furthermore, compared with multi-steptraceback according to the length of window in the traditional mode ofsliding window traceback, the control in the present disclosure issimpler, and the implementation is more convenient.

The traceback control depends on the circulation time of externaldecoding(max_times). When the external time sequence control conditionen_(—)6s&(˜en_(—)5s)=1 is met, the internal circulation count max_cnt isjudged whether to be equal to max_times, if so, decoding is stopped, andthe circulation counter(max_cnt) is zeroed; otherwise decoding isstarted again, the internal decoding start flag(trace_flag) is set as 1,and the max_cnt is added by 1. Herein, starting traceback to output thedecoded result is only a simplified expression, it actually alsocomprises address reading of the given survival path and a plurality ofoperations such as corresponding control and storage. Theoretically, themore the circulation times, the better the performance of the decoder,however, by means of emulation, when the circulation times are more thanfour circles, the performance of the decoder is improved slightly, butthe caused resource consumption is increased greatly, therefore, thevalue of the circulation time (max_times) is preferably between twocircles and four circles.

In the present embodiment, after Step S11, after data for decoding ends,six zeros may be input again, and Step S11 may be repeated. Because whenthe decoding circulation times are reached (that is, data for decodingends), in all state measurements, only one state is corresponding to themaximum accumulated path measurement value, if traceback is performed atthis time, it is necessary to store the state measurement value in eachtime of calculation in Step S11, to obtain the state measurement valuecorresponding to the maximum path measurement. In the presentdisclosure, in order to save the storage space of the state measurement,after the data for decoding ends, six zeros may be input again and StepS11 may be repeated. As the encoder comprises six shift registers, theadd-compare-select internal comparator is multiplexed, after six timesof add-compare-select calculation, the path measurement valuescorresponding to all states are equal to the maximum path measurementvalue, so that the initial state may be backtracked according to thesurvival path, that is, no state measurement value needs to be stored.It should be understood that, during the traceback in Step S12, thetraceback length is increased by 6. Therefore, in Step S12 in theembodiment, the traceback depth is two times of the encoding length plus6.

With reference to FIG. 6, in the embodiment, before Step S10, the methodfurther comprises Step S14: storing the data for decoding, which isinput externally, in a mode of interleaved memory; and reading the datafor decoding according to an external decoding instruction.

When the external decoding instruction is received, the data fordecoding, which is stored in the interleaved memories, is read indifferent time. With reference to FIG. 7, a structure diagram of aninterleaved memory is illustrated. The interleaved memory comprises twomemories SA and SB. First, the two interleaved memories are judged tocheck whether they are in idle state, if so, the new data for decodingis allowed to be written into the interleaved memories; otherwise thenew data for decoding is prohibited to be written into the interleavedmemories. It is allowed to read the data for decoding from the othermemory while the data for decoding is written into one memory. Forexample, at the time of the first scene, the input data is cached to thememory SA, and at the time of the second scene, by means of switchoverof the input data selection unit, the input data stream is cached to thememory SB, simultaneously, data in the memory SA may be sent out bymeans of selection of the output data selection unit. At the time of thethird scene, the input data stream is cached to the memory SA,simultaneously, data in the memory SB may be sent out by means ofswitchover of the output data selection unit. In this way ofcirculation, seamless buffering of data may be realized, and the postparallel processing speed is greatly improved.

In the present embodiment, according to the maximum encoding lengthsupported by the decoder, a memory structure including a group ofinterleaved memories is employed, each group may include threesingle-port RAMs respectively used for storing three paths of data g0,g1 and g2 output by the encoder. In this way, the next group of data fordecoding may be prepared simultaneously while Viterbi decoding isperformed, by means of interleaved memories, the processing delay causedby waiting for storing data during the decoding process is effectivelyreduced.

FIG. 8 is a structure diagram of a device for implementing Viterbidecoding according to one embodiment of the present disclosure.

In the embodiment, the device for implementing Viterbi decodingcomprises: a branch path measurement module 10, an add-compare-selectmodule 11 and a traceback module 12; wherein,

The branch path measurement module 10 is configured to calculate thebranch path measurement values of received code words and reference codewords;

The add-compare-select module 11 is configured to parallel accumulatethe measurement values corresponding to the states and the branch pathmeasurement values to obtain accumulated values according to a statetransition diagram, select the maximum accumulated value as the newmeasurement value of the next state, and save all survival pathselection results until the data for decoding ends;

The traceback module 12 is configured to start traceback from the finalstate to obtain the decoded data according to the survival pathselection results.

The received code words are the data for decoding, and the referencecode words are the state output values of the encoder. The branch pathmeasurement module 10 correlatively calculates the state output valuesof the encoder and the data for decoding to obtain the branch pathmeasurement values. From the encoding/decoding state transition diagramas shown in FIG. 3, by related calculation, it may be known that thebranch path measurement values from S_(k) to S_(2k) and from S_(k) toS_(2k+1) are respectively 5 and 3, and the branch path measurementvalues from S_(k+32) to S_(2k) and from S_(k+32) to S_(2k+1) arerespectively 13 and 10.

With reference to FIG. 9, the add-compare-select module 11 specificallycomprises: an accumulation unit 111, a selection unit 112, a survivalpath storage unit 113 and a judgment unit 114; wherein,

The accumulation unit 111 is configured to multi-path fully-parallelaccumulate the measurement values corresponding to the states and thebranch path measurement values to obtain the accumulated valuesaccording to the state transition diagram;

The selection unit 112 is configured to select the maximum accumulatedvalue as the new measurement value of the next state according to theadd-compare-select rule;

The survival path storage unit 113 is configured to save all survivalpath selection results;

The judgment unit 114 is configured to return to execute the nextaccumulation operation when the accumulation time is less than presetaccumulation time; and end the accumulation flow when the accumulationtime is more than or equal to the preset accumulation time.

According to the state transition diagram, by means of 32-pathfully-parallel, the accumulation unit 111 accumulates the measurementvalues corresponding to the states and the branch path measurementvalues to obtain the accumulated values. For example, at T−1 moment, themeasurement value of S_(k) is 26, the measurement value of S_(k+32) is15, and the branch path measurement values from S_(k) to S_(2k) and fromS_(k) to S_(2k+1) are respectively 5 and 3, while the branch pathmeasurement values from S_(k+32) to S_(2k) and from S_(k+32) to S_(2k+1)are respectively 13 and 10, by accumulating the measurement valuescorresponding to the states and the branch path measurement values, itmay be known that, the path accumulated values reaching S_(2k) arerespectively 26+5=31 and 15+13=28, and the path accumulated valuesreaching S_(2k+1) are respectively 26+3=29 and 15+10=25. the selectionunit 112 selects the maximum accumulated value as the new measurementvalue of the next state according to the add-compare-select rule. Thatis, it selects the maximum path accumulated value 31 as the newmeasurement value of S_(2k) and the maximum path accumulated value 29 asthe new measurement value of S_(2k+1). Simultaneously, the survival pathstorage unit 113 will save the path measurement value of each time ofselection, and the accumulation unit 111 ends the accumulation operationuntil the judgment unit 114 judges that the accumulation time is morethan or equal to the preset accumulation time.

In the embodiment, by modifying the traditional serial orserial-parallel mixed mode for calculating the accumulated pathmeasurement values to a multi-path fully-parallel calculation mode, thethroughput rate of the system data is improved, and the decoding delayis merely in us level.

With reference to FIG. 10, the add-compare-select module in theembodiment further comprises:

An anti-overflow unit 115, configured to subtract 1 from the secondaryhighest bit in the significant bits of each accumulated value to obtaina new accumulated value, if the highest bit in the significant bits ofthe accumulated path measurement value corresponding to state 0 is 1,then use the new accumulated value as the result of this accumulationoperation.

In the embodiment, when the accumulated path measurement value iscalculated, a large amount of resources will be wasted if the bit widthof the accumulated path measurement value is not limited. For example,four times of decoding circulation are performed, the length of the codeblock is 128, the bit width of the input data for decoding is 8-bit, sothe bit width of the accumulated path measurement values is 19-bit(2⁸*3*128*4=2¹⁹), at least 64 accumulated path measurement valueregisters are needed, so that the waste of resources is relativelyserious. Therefore, the anti-overflow unit 114 judges whether thehighest bit in the significant bits (if signed digits are available,significant bits are data bits other than sign bits) of the eachaccumulated path measurement value corresponding to state 0 is 1, if so,it respectively subtracts the secondary highest bit in the significantbits of all obtained accumulated values by 1, that is, it simplynormalizes the whole measurement values to zero. For example, by taking14-bit accumulated path measurement values as example, whendistance0[12] is zero, normal operation is performed, and the generatedsubtraction enabling signal sub_en is in low level; when distance0[12]is 1, the generated subtraction enabling signal sub_en is in high level,so that all survival paths are subtracted by 0x800 (hexadecimal), i.e.,the secondary highest bit in the significant bits of distance0, toprevent the overflow of the accumulated measurement values effectively.

The traditional anti-overflow step mainly depends on the selection ofthe fixed value, and it is necessary to compare all path measurementvalues and select the minimum one as the fixed value, instead, theanti-overflow step in the embodiment may save a lot of comparison, andselection circuits and the subtraction circuit is quite simple as it isonly aimed at subtracting the three top bits of the accumulatedmeasurement value by 1.

In the embodiment, in the traceback module 12, the traceback depth istwo times of the encoding length. The specific traceback process is:from Step S11, the initial state of traceback may be obtained asmax_num[5:0]=0, the front state of the initial state ismax_num[5:0]={qqq[max_num], max_num[5:1]}, herein, qqq is the recorded64-bit survival path value. When the recorded survival path selectionresult qqq has to be selected for traceback, the traceback depth isabout 2*block_size, the output result of decoding after traceback isdec_bit=max_num[0]. When the data is output, traceback data obtained ina depth the first time of the encoding length is abandoned, onlytraceback data obtained in a depth the second time of the encodinglength is used, therefore, the traceback data obtained in a depth onlyone time of the encoding length is stored, no much thing is added interms of resources. The reason for the application of traceback depththat is two times of the encoding length is that, normal convolutionalcodes are replaced with tail biting convolutional codes in thehigh-speed decoding system, after emulation, it is found that theperformance of the decoder is improved by 0.2 db to 0.3 db in comparisonwith traceback in a depth that is one time of the encoding length,therefore, in the disclosure, the application of traceback depth that istwo times of the encoding length guarantees the performance of thesystem. Furthermore, compared with multi-step traceback according to thelength of window in the traditional mode of sliding window traceback,the control in the disclosure is simpler, and the implementation is moreconvenient.

In the embodiment, the add-compare-select module 11 is furtherconfigured to, after data for decoding ends, input six zeros again andrepeat the accumulation operation of the path measurement values.Because when the decoding circulation times are reached (that is, datafor decoding ends), in all state measurements, only one state iscorresponding to the maximum accumulated path measurement value, iftraceback is performed at this time, it is necessary to store the statemeasurement value in each time of add-compare-select calculation of theadd-compare-select module 11, to obtain the state measurement valuecorresponding to the maximum path measurement. Therefore, in thedisclosure, in order to save the storage space of the state measurement,after data for decoding ends, six zeros are input again, and theaccumulation of the path measurement value is repeated. As the encoderincludes six shift registers, after six times of add-compare-selectcalculation, the path measurement values corresponding to all states areequal to the maximum path measurement value, so that the initial statemay be backtracked according to the survival path, that is, no statemeasurement value needs to be stored. It should be understood that, whentraceback is performed in allusion to the results saved in theadd-compare-select module 11, the traceback length is increased by 6.Therefore, in the embodiment, the traceback depth employed by thetraceback module 12 is two times of the encoding length plus 6.

With reference to FIG. 11, a structure diagram of a device forimplementing Viterbi decoding in still another embodiment of thedisclosure is illustrated.

On the basis of the above embodiment, the device for implementingViterbi decoding in the embodiment further comprises:

An input data storage module 13, configured to store the data fordecoding, which is input externally, in a mode of interleaved memory;and read the data for decoding according to an external decodinginstruction.

When the external decoding instruction is received, the data fordecoding, which is stored in the interleaved memories, is read indifferent time. The input data storage module 13 comprises a group ofinterleaved memories, each group of memories consists of three smallstorage areas (for example, single-port RAM) respectively used forstoring three paths of data g0, g1 and g2 output after being encoded.First, the interleaved memories are judged to check whether they are inidle state, if so, new data for decoding is allowed to be written intothe interleaved memories; otherwise new data for decoding is prohibitedto be written into the interleaved memories. It is allowed to read datafor decoding from the other memory while data for decoding is writteninto one memory. The input data storage module 13 is mainly controlledby an external time sequence control module to send input data to thebranch path measurement module 10 in parallel. Therefore, the next groupof data for decoding may be prepared simultaneously while Viterbidecoding is performed, by means of interleaved memories, the processingdelay caused by waiting for storing data during the decoding process iseffectively reduced.

The descriptions above are only the preferable embodiment of the presentdisclosure, which are not used to restrict the present disclosure. Forthose skilled in the art, the present disclosure may have variouschanges and variations. Any amendments, equivalent substitutions,improvements, etc. within the principle of the present disclosure areall included in the scope of the protection of the present disclosure.

What is claimed is:
 1. A method for implementing Viterbi decoding,comprising: calculating branch path measurement values of received codewords and reference code words; parallel accumulating the branch pathmeasurement values and measurement values corresponding to states toobtain accumulated values according to a state transition diagram,selecting a maximum accumulated value as a new measurement value of anext state, and saving all survival path selection results until datafor decoding ends; starting traceback from a final state to obtaindecoded data according to the survival path selection results; andwherein parallel accumulating the branch path measurement values and themeasurement values corresponding to the states to obtain the accumulatedvalues according to the state transition diagram, selecting maximumaccumulated value as the new measurement value of the next state, andsaving all survival path selection results until the data for decodingends comprises: multi-path fully-parallel accumulating the branch pathmeasurement values and the measurement values corresponding to thestates to obtain the accumulated values according to the statetransition diagram; selecting the maximum accumulated value as the newmeasurement value of the next state according to the add-compare-selectrule, and saving all survival path selection results; and returning toexecute a next accumulation operation when an accumulation time is lessthan a preset accumulation time and ending the accumulation flow whenthe accumulation time is more than or equal to the preset accumulationtime.
 2. The method for implementing Viterbi decoding according to claim1, wherein before calculating the branch path measurement values of thereceived code words and the reference code words, the method furthercomprises: storing the data for decoding, which is input externally, ina mode of interleaved memory; and reading the data for decodingaccording to an external decoding instruction.
 3. The method forimplementing Viterbi decoding according to claim 1, wherein aftermulti-path fully-parallel accumulating the branch path measurementvalues and the measurement values corresponding to the states to obtainthe accumulated values according to the state transition diagram, themethod further comprises: subtracting 1 from the secondary highest bitin the significant bits of each accumulated value to obtain a newaccumulated value, if the highest bit in the significant bits of theaccumulated value corresponding to state 0 is 1, then using the newaccumulated value as the result of this accumulation operation.
 4. Themethod for implementing Viterbi decoding according to claim 1, whereinthe traceback depth is two times of the encoding length.
 5. A device forimplementing Viterbi decoding, comprising: a branch path measurementmodule, an add-compare-select module and a traceback module; wherein,the branch path measurement module is configured to calculate branchpath measurement values of received code words and reference code words;the add-compare-select module is configured to parallel accumulate thebranch path measurement values and measurement values corresponding tostates to obtain accumulated values according to a state transitiondiagram, select a maximum accumulated value as a new measurement valueof a next state, and save all survival path selection results until datafor decoding ends; the traceback module is configured to start tracebackfrom a final state to obtain decoded data according to the survival pathselection results; and wherein the add-compare-select module comprises:an accumulation unit, a selection unit, a survival path storage unit anda judgment unit; wherein the accumulation unit is configured tomulti-path fully-parallel accumulate the branch path measurement valuesand measurement values corresponding to the states to obtain theaccumulated values according to the state transition diagram; theselection unit is configured to select the maximum accumulated value asthe new measurement value of the next state according to theadd-compare-select rule; the survival path storage unit is configured tosave all survival path selection results; and the judgment unit isconfigured to return to execute a next accumulation operation of theaccumulation unit when an accumulation time is less than a presetaccumulation time and end the accumulation flow when the accumulationtime is more than or equal to the preset accumulation time.
 6. Thedevice for implementing Viterbi decoding according to claim 5, furthercomprising: an input data storage module, configured to store the datafor decoding, which is input externally, in a mode of interleavedmemory; and read the data for decoding according to an external decodinginstruction.
 7. The device for implementing Viterbi decoding accordingto claim 5, wherein the add-compare-select module further comprises: ananti-overflow unit, configured to subtract 1 from the secondary highestbit in the significant bits of each accumulated value to obtain a newaccumulated value, if the highest bit in the significant bits of theaccumulated value corresponding to state 0 is 1, then use the newaccumulated value as the result of this accumulation operation.
 8. Thedevice for implementing Viterbi decoding according to claim 5 whereinthe traceback depth employed by the traceback module is two times theencoding length.
 9. The method for implementing Viterbi decodingaccording to claim 2, wherein the traceback depth is two times theencoding length.
 10. The method for implementing Viterbi decodingaccording to claim 6, wherein the traceback depth is two times theencoding length.
 11. The device for implementing Viterbi decodingaccording to claim 6 wherein the traceback depth employed by thetraceback module is two times the encoding length.
 12. The device forimplementing Viterbi decoding according to claim 7 wherein the tracebackdepth employed by the traceback module is two times the encoding length.